An Asynchronous IEEE Floating-Point Arithmetic Unit
Abstract
An asynchronous floating-point arithmetic unit is designed and tested at the transistor level using Cadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differential cascode voltage switch) logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data and single-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit) addition/subtraction, multiplication, division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, with rounding and other operations to be handled by separate hardware or software. Division and remainder are done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptions are noted by flags (and not trap handlers) and the output is in single-precision.
Previous work on asynchronous floating-point arithmetic units have mostly focused on single operations such as division. This is the first work to the authors' knowledge that can perform floating-point addition, multiplication, division, and remainder using a common datapath.
Published
2008-01-15
How to Cite
NOCHE, Joel R.; ARANETA, Jose C..
An Asynchronous IEEE Floating-Point Arithmetic Unit.
Science Diliman: A Journal of Pure and Applied Sciences, [S.l.], v. 19, n. 2, jan. 2008.
ISSN 2012-0818.
Available at: <https://journals.upd.edu.ph/index.php/sciencediliman/article/view/711>. Date accessed: 03 aug. 2025.
Issue
Section
Articles
Keywords
Asynchronous logic circuits; floating point arithmetic; calculation times
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