A Study of Translation Look Aside Buffer Structures for Low Power Consumption

Abstract

Modern microprocessors consume large amounts of energy, majority of which comes from the processor’s clock and memory hierarchy. One particular area that can be explored for possible power reduction is the translation lookaside buffer (TLB). TLBs are small caches used to speed up virtual-to-physical address translation. The aim of this study is to design and implement different TLB design structures using VHDL. The structures are laid-out using 0.25 μm CMOS standard cells and then analyzed and characterized in terms of area, performance and power consumption. Results show that, compared to the different structures considered in this study, fully associative structures consume the least amount of power and produce the lowest miss rate. Banked associative structures, on the other hand, occupy the smallest silicon area, with a power consumption that is slightly higher than that of a fully associative structure.