Analysis of Crack Propagation Under Different Die Tilt Configuration on a Small Outline Transistor

Abstract

Abstract — In today’s microelectronic industry, the increasing demand for miniaturization and high function integration poses a big challenge in maintaining the reliability of the package. It was found out that majority of the reliability problems can be attributed to thermal and mechanical loadings during manufacturing and assembling process. Die cracking and die tilting are two of the most common defects originating from this process that affect the reliability of the electronic packages. This study aims to investigate the influence of die tilting to the propensity of crack propagation on the silicon die. In this research, the cooling phase of the die and clip attach reflow of small outline transistor was simulated using a finite element-based software. An initial crack was incorporated in the silicon die model to show the imperfections acquired during manufacturing stage. J-integral (J) parameter of fracture mechanics was employed as a criterion for the behavior of incipient cracks. With the assumption that the die used in this study exhibits linear elastic, isotropic property, the calculated J-integral values were correlated to the energy release rate (G). The simulation results showed that as the tilt angle increases, there is also a significant increase in the value of J-integral. The highest J value was observed on the maximum tilt angle. Moreover, this study presents clear relationship between the die strength and the specified failure factors; crack and tilt.

Keywords — Fracture Mechanics, ANSYS, Crack Propagation