Investigation of Silicon Die Crack for Varying Silicon Die Parameters and Die Attach Material

Hannah Erika Macaspac Department of Mechanical Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines
Jennifer Callanga Department of Mechanical Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines
Richard Raymond Dimagiba Department of Mechanical Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines
Manolo Mena Department of Mining, Metallurgical, and Materials Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines

Abstract

Abstract— Demand for small sized, portable electronic devices continually increases until today. Compact electronics would mean a reduction in size of semiconductors that would translate to further shrinking of components inside of it such as the small outline diode (SOD) and the small outline transistor (SOT). This work utilized the finite element method with a fracture mechanics approach to analyze the effect of varying geometric parameters on the J-integral of an induced crack on the silicon die. Furthermore, investigation of the effect of two die attach materials, having different modulus of elasticity, on the crack propensity on the silicon die was done. The J-integral values obtained generally showed a peak value with the mid-sized silicon die whose die attach material has higher modulus of elasticity. The J-integral value generally decreased with die thickness but was found to be minimum at around 100 mm die thickness. A further reduction in thickness resulted in an increase in J-integral. Results from the simulations will aid in determining the effect of these parameters on the reliability of the package with respect to die crack risk and can be utilized to guide improvements on the existing package design.

Keywords—die crack, J-integral, small-outline transistor

Published

2020-06-24

Issue

Vol 41 No 1 (2020)

Section

Articles