Optimizing a 32-Bit ARM7 Microprocessor

J C. Delarmente Electrical and Electronics Engineering, College of Engineering, University of the Philippines
LA P. Gahol Electrical and Electronics Engineering, College of Engineering, University of the Philippines
CE L. Paragas Electrical and Electronics Engineering, College of Engineering, University of the Philippines
John Richard E. Hizon Electrical and Electronics Engineering, College of Engineering, University of the Philippines
Anastacia P. Ballesil Electrical and Electronics Engineering, College of Engineering, University of the Philippines

Abstract

The ARM7 belongs to the Advanced RISC Machines (ARM) family of general-purpose 32-bit microprocessors. Its architecture is based on Reduced Instruction Set Computer (RISC) principles, and employs a three-stage pipeline which results in performance speedup by increasing the microprocessor’s throughput.

A previous high-level implementation of the base ARM7 at the Intel Microprocessor Laboratory has a maximum usable clock frequency of 10MHz which is quite slow for a 32-bit processor. The goal of this new implementation was to improve processor speed of the original ARM7 via four techniques, namely: changing the coding style, using one-hot encoding, applying slack borrowing, and adapting architectural modifications.

As with the original, the implementation employed two levels of abstraction, namely Behavioral Level and Register Transfer Level (RTL). The RTL model was synthesized using standard cells on a 0.25μm CMOS process. Synthesis and verification was performed using Cadence Design Systems Software. The performance of this new implementation was evaluated not only for speed but also for area and power consumption. Power measurements were done using Synopsys PrimePower. The maximum clock frequency is 40MHz, area is measured to be 0.99570 mm2, and observed maximum power is 43.58mW.

Published

2021-08-05

Issue

Vol 32 No 1 (2011)

Section

Articles