A Design Methodology for Implementing RF CMOS Low-Noise Amplifiers in a 0.25 µM CMOS Process

Abstract

In this paper, a methodology in designing CMOS Low-Noise Amplifiers (LNAs) in a 0.25-µm CMOS process is proposed. Three power-matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stability. Twenty-two LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. These circuits differ from each other in terms of the transistor dimensions, inductor and capacitor implementations, and bias voltages used. The performance of LNA circuits designed using the three different techniques are characterized. Simulation and actual measurement results are also compared and analyzed to determine the capability of the simulator to predict the LNA’s overall performance at radio frequencies.