32-Bit Pipelined RISC Microprocessor

Abstract

The design of microprocessors is a crucial step in determining the over-all performance of a processing system. A design technique may lead to several improvements in one aspect of processor performance, but it may also worsen other aspects.

In terms of the design of the instruction set, there are mainly two approaches of processor design. The first approach called Complex Instruction Set Computers (CISC), uses a few commands to implement complex instructions. Ideally, this leads to shorter programs. The other approach, called Reduced Instruction Set Computer (RISC), uses simple instructions to perform complex tasks.

A key advantage of RISC over CISC is its suitability for pipelining. Since the RISC approach implements simple instructions only, processing of instructions can de done in a parallel manner. This implies that more operations can be executed as a single instruction cycle. Hence, the technique of pipelining leads to higher throughput.

The project aims to convert an existing implementation of a 16-bit non-pipelined RISC microprocessor. The improvement of the previous project in terms of execution speed would be given focus so the layout size would have to be sacrificed. The speed of the pipelined processor in executing a simple test would have to be sacrificed. The speed of the pipelined processor in executing simple test bubble-sorting algorithm will be compared to that of the former project and the Motorola 6800. Simulations and the design itself would be implemented using CADENCE and Visual HDL 5.2.